Data communications is the transmission of data from one computer or device to another. A Universal Serial Bus is an external peripheral interface standard for data communications between a computer and external peripherals. A Universal Serial Bus follows a data communications protocol defined in the Universal Serial Bus (USB) specification version 1.1.
Recently, a USB specification version 2.0 was made available. USB specification version 1.1 supports two different rates for transmitting data: 1.5 megabits per second (Mbps) for low-speed devices and 12 Mbps for high-speed devices. USB specification 2.0 extends the rate for transferring data from 12 Mbps on USB 1.1 up to 480 Mbps on USB 2.0.
In some digital data communication arrangements, incoming received serial data bit streams must be processed faster than the frequency of the available clock. In serial digital communications, this can be characterized as the problem of processing more than one bit of information per unit bit time. Parallel concurrent techniques that process more than one serial data bit per unit bit time are needed to solve this problem. In particular, a USB 2.0 transmitting device transmits digital bits over a USB cable at a rate of 480 MHz (2.08 nsec). This high frequency makes it very difficult for a USB receiving device to process incoming bits at the frequency that the transmitter used to transmit the USB data bits. The USB 2.0 specification does not provide a technique to solve this problem thus a novel parallel, concurrent bit processing technique is needed for processing incoming data from a USB 2.0 transmitting device.
It is also common in some digital data communication arrangements for incoming serial data streams to be received in the form of packets which contain a very specific serial data pattern that delineates a start of packet (SOP). However, a problem encountered in digital communication using USB is detecting the first received bit of an incoming packet from the incoming serial data stream. The USB 2.0 specification provides a specific SOP pattern that indicates which bit in the data stream is the first bit of the USB data packet, but it does not provide a technique to detect the SOP pattern. Once the SOP is detected, the incoming bit stream must be aligned into eight bit fields of data that can be assembled byte by byte into a packet for use by upstream USB devices as further described in U.S. patent application Ser. No. 09/866,150 entitled “Concurrent Asynchronous USB Data Stream Destuffer With Variable Width Bit-Wise Memory Controller” which is assigned to the assignee of the present invention. Providing a technique to detect the SOP in the received data stream is further complicated by the 480 MHz bit rate of the incoming data stream. A technique is needed to detect a USB 2.0 SOP pattern and to align the USB data.
It is also common in some digital data communication arrangements for incoming serial data streams to be received in the form of encoded data bits that must be decoded prior to being utilized by functions that reside further upstream from the received bits. Since the USB 2.0 transmitter NRZI (NonReturn-to-Zero Inverted) encodes each bit prior to transmission on the USB wire, the received bit stream must be decoded as the bits are assembled into USB packets for use by upstream functions that are not able to utilize NRZI encoded data. A technique is needed to perform this NRZI decode operation after the USB data stream SOP has been detected and as the data stream is being parsed into a packet.
As described above, currently available USB 1.1 peripheral implementations run at a maximum data rate of 12 Mbps and use a 12 MHz clock to process the incoming data stream using bit level state machines. If this approach is also used in USB 2.0, bit level state machines running at 480 MHz would be needed. Processing incoming data at this clock rate would present very difficult design challenges and add significant cost to the peripheral controller. Therefore, there is a need for a system that is capable of processing incoming USB 2.0 data at a faster rate without substantially increasing the implementation costs and complexity.